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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 1:16 RECEIVER BiCMOS LVPECL OC-48 TRANSMITTER CLOCK GENERATOR SONET/SDH/ATM OC-12 1:16 RECEIVER AND RECEIVER GENERAL DESCRIPTION
S3044 S3044 S3044
FEATURES
* Micro-power Bipolar technology * Complies with Bellcore and ITU-T specifications * Supports 2.488 GHz (OC-48) * Interface to both LVPECL and TTL logic * 16-bit LVPECL data path * Compact 80 PQFP/TEP package * Diagnostic loopback mode * Line loopback * Signal detect input * Low jitter LVPECL interface * Single 3.3 V supply
The S3044 SONET/SDH Demux chip is a fully integrated deserialization SONET OC-48 (2.488 GHz) interface device. The chip performs all necessary serial-to-parallel and framing functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based ATM applications. Figure 1 shows a typical network application. The low jitter LVPECL interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3044 is packaged in a 80 PQFP/TEP, offering designers a small package outline.
APPLICATIONS
* * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters Add drop multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
Network Interface Processor
16
S3043 Tx S3044 Rx
OTX
ORX
S3040
S3044 Rx S3043 Tx
16
16
16
S3040
ORX
OTX
December 8, 2000 / Revision H
Network Interface Processor
1
S3044 S3044 OVERVIEW
The S3044 receiver implements SONET/SDH deserialization and frame detection functions. The block diagram in Figure 2 shows the basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes serial-to-parallel conversion and system timing. The system timing circuitry consists of management of the datastream, framing, and clock distribution throughout the front end.
SONET/SDH/ATM OC-48 1:16 RECEIVER
The sequence of operations of the S3044 is as follows:
Receiver Operations: 1. Serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 16-bit parallel output Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figures 7 through 9. Internal clocking and control functions are transparent to the user. Suggested Interface Devices
AMCC AMCC S3040 S3043 Clock Recovery Device OC-48 Transmitter
Figure 2. S3044 Functional Block Diagram
SDPECL
1:16 SERIAL TO PARALLEL
16
POUT[15:0]
KILLRXCLK OOF FRAMEN DLEB RSDP/N LSDP/N
2 D 2 2 2 D
8 2
TIMING FRAME GEN BYTE DETECT
RX155MCKP/N POCLKP/N FP SEARCH
2 1
2
LLDP/N
M U X M U X
RSCLKP/N LSCLKP/N
2
LLCLKP/N
LLEB RSTB
Vbb
OVREF
2
December 8, 2000 / Revision H
SONET/SDH/ATM OC-48 1:16 RECEIVER SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 3 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Data Rates and Signal Hierarchy Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical carrier level-N signal (OC-N). The S3044 chip supports OC-48 rate (2.488 Gbps). Frame and Byte Boundary Detection
S3044
The SONET/SDH fundamental frame format for STS-48 consists of 144 transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 144 overhead and 4176 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 4.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Figure 3. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Layer Overhead (Embedded Ops Channel) Path layer Line layer Section layer Path layer Line layer Section layer
576 Kbps
192 Kbps
Photonic layer
Photonic layer 0 bps
End Equipment
Fiber Cable End Equipment
Table 1. SONET Signal Hierarchy
Elec. STS-1 STS-3 STS-12 STS-24 STS-48 STM-1 STM-4 STM-8 STM-16 CCITT Optical OC-1 OC-3 OC-12 OC-24 OC-48 Data Rate (Mbps) 51.84 155.52 622.08 1244.16 2488.32
Figure 4. STS-48/OC-48 Frame Format
A1 A1
9 Rows
A1 A1 48 A1 Bytes
A2 A2
A2 A2 48 A2 Bytes
Transport Overhead 144 Columns 144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns 4176 x 9 = 37,584 bytes
s
125 sec
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s
3
S3044
RECEIVER OPERATION
The S3044 receiver chip provides the first stage of digital processing of a receive SONET STS-48 bitserial stream. It converts the bit-serial 2.488 Gbps data stream into a 155.52 Mbyte/sec byte-serial data format. A loopback mode is provided for diagnostic loopback (transmitter to receiver). A Line Loopback (receiver to transmitter) is also provided. Frame and Byte Boundary Detection The Frame and Byte Boundary Detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by one A2 byte. Framing pattern detection is enabled and disabled by the FRAMEN input. Detection is enabled by a rising edge on OOF when FRAMEN is active. It is disabled when a framing pattern is detected. When framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (RSD or looped transmitter data). During this time, the parallel data bus (POUT [15:0]) will not contain valid data. The timing generator block takes the located byte boundary and uses it to block the incoming data stream into bytes for output on the parallel output data bus (POUT[15:0]). The frame boundary is reported on the frame pulse (FP) output when any 32-bit pattern matching the framing pattern is detected on the incoming data stream. When framing pattern detection is disabled, the byte boundary is frozen to the location found when detection was previously enabled. Only framing patterns aligned to the fixed byte boundary are indicated on the FP output. The probability that random data in an STS-48 stream will generate the 32-bit framing pattern is extremely small. It is highly improbable that a mimic pattern would occur within one frame of data. Therefore, the time to match the first frame pattern and to verify it with down-stream circuitry, at the next occurrence of the pattern, is expected to be less than the required 250 s, even for extremely high bit error rates.
SONET/SDH/ATM OC-48 1:16 RECEIVER
Serial to Parallel Converter The Serial to Parallel Converter consists of three 16-bit registers. The first is a serial-in, parallel-out shift register, which performs the serial to parallel conversion. The second is an 16-bit internal holding register, which transfers data from the serial to parallel register on byte boundaries as determined by the frame and byte boundary detection block. On the falling edge of the free running POCLK, the data in the holding register is transferred to an output holding register which drives POUT[15:0].
OTHER OPERATING MODES
Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output clock and data from the transmitter (LSCLK and LSD) is routed to the serial-to-parallel block in place of the normal data stream (RSCLK and RSD). Line Loopback The Line Loopback circuitry consists of alternate clock and data output drivers. When LLEB is active, it enables the Line Loopback output data and clock (LLD and LLCLK), and a receive-to-transmit loopback can be established at the serial data rate.
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SONET/SDH/ATM OC-48 1:16 RECEIVER
Table 2. Input Pin Assignment and Description
Pin Name RSDP RSDN Level Internally Biased Diff. LVPECL Internally Biased Diff. LVPECL Externally Biased Diff. LVPECL Externally Biased Diff. LVPECL LVTTL I/O I Pin # 3 4 Description
S3044
Receive Serial Data. Serial data stream signals normally connected to an optical receiver module. These inputs are clocked by the RSCLK inputs. Internally biased and terminated. Receive Serial Clock. Recovered clock signal that is synchronous with the RSD inputs. This clock is used by the receive section as the master clock to perform framing and deserialization functions. Internally biased and terminated. Loopback Serial Data. Serial data stream signals normally connected to the transmitter for loopback testing. These inputs are clocked by the LSCLK inputs. Internally terminated. Loopback Serial Clock. Clock input from the transmitter that is synchronous with the LSD inputs. This clock is used during local loopback testing to perform the framing and deserialization functions. Internally terminated. Out of Frame. Indicator used to enable framing pattern detection logic in the S3044. The framing pattern detection logic is enabled by a rising edge on OOF, and remains enabled until frame boundary is detected. OOF is an asynchronous signal with a minimum pulse width of one POCLK period. (See Figures 10 and 11.) LVPECL Signal Detect. Active High. A single-ended LVPECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDPECL is inactive, the data on the Serial Data In (RSDP/N) pins will be internally forced to a constant zero. When SDPECL is active, data on the RSDP/N pins will be processed normally. Diagnostic Loopback Enable. Selects diagnostic loopback. Active Low. When DLEB is inactive, the S3044 device uses the primary data (RSD) and clock (RSCLK) inputs. When active, the S3044 device uses the diagnostic loopback clock and data from the transmitter. Master Reset. Reset input for the device, active Low. During reset, POCLK does not toggle. Line Loopback Enable. Selects Line Loopback. Active Low. When LLEB is low, the S3044 will enable the data from the LLD/LLCLK outputs. Kill Receive Clock Input. For normal operation set KILLRXCLK "High." When this input is low, it will force RX155 MCK and POCLK outputs to a logic "0" state. Frame Enable Input. For normal operation set FRAMEN High. This enables the frame detector circuit to detect A1 A2 alignment and lock to word boundary. When this input is Low, it will disable the frame detector circuit and it will lock on the last byte alignment state.
RSCLKP RSCLKN
I
7 8
LSDP LSDN
I
74 73
LSCLKP LSCLKN
I
80 79
OOF
I
16
SDPECL SingleEnded LVPECL
I
19
DLEB
LVTTL
I
23
RSTB
LVTTL
I
24
LLEB
LVTTL
I
22
KILLRXCLK
LVTTL
I
18
FRAMEN
LVTTL
I
17
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S3044
Table 3. Output Pin Assignment and Description
Pin Name POUTP0 POUTP1 POUTP2 POUTP3 POUTP4 POUTP5 POUTP6 POUTP7 POUTP8 POUTP9 POUTP10 POUTP11 POUTP12 POUTP13 POUTP14 POUTP15 LLDP LLDN LLCLKP LLCLKN FP Level SingleEnded LVPECL I/O O Pin # 32 33 34 35 36 37 38 39 43 44 45 46 47 48 49 50 62 61 69 68 30
SONET/SDH/ATM OC-48 1:16 RECEIVER
Description Parallel Output. Parallel data bus, a 155.52 Mbyte/sec 16-bit word, aligned to the parallel output clock (POCLK). POUT<15> is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). POUT<0> is the least significant bit (corresponding to bit 16 of each PCM word, the last bit received). POUT<15:0> is updated on the falling edge of POCLK.
Low Swing Diff. CML Low Swing Diff. CML SingleEnded LVPECL
O
Line Loopback Data. A retimed version of the incoming data stream [RSD]. Enabled by LLEB. Line Loopback Clock. A buffered version of the RSCLK or LSCLK input. Enabled by LLEB. Frame Pulse. Indicates frame boundaries in the incoming data stream. If framing pattern detection is enabled, as controlled by the OOF input, FP pulses high for one POCLK cycle when a 32-bit sequence matching the framing pattern is detected on the serial data inputs. When framing pattern detection is disabled, FP pulses high when the incoming data stream, after byte alignment, matches the framing pattern. FP is updated on the falling edge of POCLK. Parallel Output Clock. A 155.52 MHz nominally 50% duty cycle, byte rate output clock, that is aligned to POUT<15:0> byte serial output data. POUT<15:0> and FP are updated on the falling edge of POCLK. A1 A2 Frame Search Output. A High on this output pin indicates the frame detection circuit is activated and it is searching for a new A1 A2 byte alignment. This output will be High during the entire period of A1 A2 frame search. Once a new alignment is found, this signal will remain High for a minimum of one 155 MHz clock period beyond the third A2 byte before it will be set to Low. Receive Free Running 155 MHz Clock Output. This clock is generated by dividing the RSCLK signal by sixteen. Single-Ended LVPECL reference voltage. Tracks midswing voltage of parallel output data bus.
O
O
POCLKP POCLKN
Diff. LVPECL
O
51 52
SEARCH
LVTTL
O
25
RX155MCKP RX155MCKN OVREF
Diff. LVPECL DC O
28 29 31
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SONET/SDH/ATM OC-48 1:16 RECEIVER
Table 4. Common Pin Assignment and Description
Pin Name COREGND COREVCC LVPECLVCC Level GND +3.3V +3.3V I/O Pin # 10, 12, 14, 55 9, 11, 13, 56 Core Ground Core VCC Description
S3044
1, 5, 26, LVPECL VCC 42, 54, 64, 67, 72, 76, 78 2, 6, 27, 40, 41, 53, 63, 66, 71, 75, 77 15 21 20 57, 58, 59, 60, 65, 70 LVPECL Ground
LVPECLGND
GND
LVTTLVCC LVTTLGND THD NC
+3.3V GND
TTL VCC TTL Ground Thermal Diode Not Connected
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S3044
Figure 5. S3044 Pinout
SONET/SDH/ATM OC-48 1:16 RECEIVER
LVPECLVCC LVPECLGND RSDP RSDN LVPECLVCC LVPECLGND RSCLKP RSCLKN COREVCC COREGND COREVCC COREGND COREVCC COREGND LVTTLVCC OOF FRAMEN KILLRXCLK SDPECL THD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
LSCLKP LSCLKN LVPECLVCC LVPECLGND LVPECLVCC LVPECLGND LSDP LSDN LVPECLVCC LVPECLGND NC LLCLKP LLCLKN LVPECLVCC LVPECLGND NC LVPECLVCC LVPECLGND LLDP LLDN
S3044 80 PQFP/TEP TOP VIEW
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC NC NC NC COREVCC COREGND LVPECLVCC LVPECLGND POCLKN POCLKP POUTP15 POUTP14 POUTP13 POUTP12 POUTP11 POUTP10 POUTP9 POUTP8 LVPECLVCC LVPECLGND
8
LVTTLGND LLEB DLEB RSTB SEARCH LVPECLVCC LVPECLGND RX155MCKP RX155MCKN FP OVREF POUTP0 POUTP1 POUTP2 POUTP3 POUTP4 POUTP5 POUTP6 POUTP7 LVPECLGND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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SONET/SDH/ATM OC-48 1:16 RECEIVER
Figure 6. 80 PQFP/TEP Package
S3044
BOTTOM VIEW TOP VIEW
Note: The S3044 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not appear in the area immediately under the package. This heatsink is electrically biased to the Vee potential of the S3044. For optimum thermal management, a foil surface at ground (or Vee if other than ground) is recommended immediately under the package, and connected with multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a good thermal dissipation path.
Table 5. Thermal Management
Device S3044 Max Package Power 1.25 W jc 2.1C/W ja 26C/W
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S3044
SONET/SDH/ATM OC-48 1:16 RECEIVER
Table 6. Low Swing Differential CML Output DC Characteristics
Parameters VOL VOH VOUTDIFF VOUTSINGLE Description Low Swing CML Output LOW Voltage Low Swing CML Output HIGH Voltage Low Swing CML Serial Output Differential Voltage Swing Low Swing CML Serial Output Single-ended Voltage Swing Min Vcc -0.50 Vcc -0.20 360 180 Typ Max Vcc -0.25 Vcc -0.05 800 400 Units V V mV mV Conditions 100 line-to-line. 100 line-to-line. 100 line-to-line. 100 line-to-line.
Table 7. Internally Biased Differential LVPECL Input DC Characteristics
Parameters VBIAS VINDIFF VINSINGLE RDIFF Description LVPECL DC Bias Voltage Differential Input Voltage Swing Differential Input Single-Ended Swing Differential Input Resistance Min Vcc -1.2 300 150 80 100 Typ Max Vcc -0.8 1200 600 120 Units V mV mV Conditions Inputs open. See Figure 13. See Figure 13.
Table 8. Externally Biased Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE RDIFF Description LVPECL Input LOW Voltage LVPECL Input HIGH Voltage Differential Input Voltage Swing Differential Input Single-Ended Swing Differential Input Resistance Min Vcc -2.000 Vcc -1.20 30 0 150 80 100 Typ Max Vcc -0.25 Vcc -0.05 1200 600 120 Units V V mV mV See Figure 13. See Figure 13. Conditions
Table 9. Single Ended LVPECL Input DC Characteristics
Parameters VIL VIH Description LVPECL Input Low Voltage LVPECL Input High Voltage Min Vcc -2.30 Vcc -1.250 Typ Max Vcc -1.441 Vcc -0.570 Units V V Conditions
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Table 10. Single Ended LVPECL Output DC Characteristics
Parameters VOL VOH Description LVPECL Output Low Voltage LVPECL Output High Voltage Min Vcc -2.2 Vcc -1.20 Typ Max Vcc -1.50 Vcc -0.65 Units V V Conditions
S3044
220 to GND, 82 to Vcc and 130 to GND 220 to GND, 82 to Vcc and 130 to GND Absolute limits over temperature. At a given temperature OVREF tracks VOH and VOL :
OVREF
Single Ended LVPECL DC Bias Voltage
Vcc -1.80
Vcc -1.20
V
OVREF = VOH + VOL 120mV 2
Table 11. Low Speed Differential LVPECL Input DC Characteristics
Parameters VIL VIH VINDIFF VINSINGLE Description LVPECL Input Low LVPECL Input High Diff. Input Voltage Swing Differential Input Single-Ended Swing Min Vcc -2.0 Vcc -1.2 400 200 Max Vcc -0.5 Vcc -0.3 2000 1000 Units V V mV mV See Figure 13. See Figure 13. Comments
Table 12. Low Speed Differential LVPECL Output DC Characteristics
Parameters VOUTSINGLE VOUTDIFF VOH VOL Description Single Ended Output Voltage Swing Diff. Output Voltage Swing Output High Voltage Output Low Voltage Min 550 1100 Vcc -1.15 Vcc -1.95 Max 950 1900 Vcc -0.60 Vcc -1.50 Units mV mV V V Comments 220 to GND and 100 line-to-line 220 to GND and 100 line-to-line 220 to GND and 100 line-to-line 220 to GND and 100 line-to-line
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S3044
Table 13. LVTTL Input/Output DC Characteristics
Symbol VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage -500 2.2 Min 2.0 0.0 Ty p
SONET/SDH/ATM OC-48 1:16 RECEIVER
Max TTL VCC 0.8 50
Unit V V A A V
Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min VIL = Max IOH = -100 A VIH = Min VIL = Max IoL = 4 mA
VOL
Output Low Voltage
0.5
V
Table 14. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on Vcc with Respect to GND Voltage on any LVPECL Input Pin Voltage on any LVTTL Input Pin High Speed LVPECL Output Source Current Min -65 -0.5 0 -0.5 Typ Max 150 +5.0 Vcc +5.5 50 Units C V V V mA
ESD Ratings The S3044 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 2000 V except pin 61, pin 62, pin 68, and pin 69.
Table 15. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on Vcc with Respect to GND Voltage on any LVPECL Input Pin Voltage on any LVTTL Pin Min -40 -40 3.13 Vcc-2 0 3.3 Typ Max 85 +130 3.47 Vcc 5.5 Units C C V V V
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Table 16. Power Consumption
Parameter ICC1
1. Add 70mA for loopback active.
S3044
Min
Typ 300
Max 360
Units mA
Conditions Outputs open
Table 17. AC Receiver Timing Characteristics
Symbol POCLK Duty Cycle tPPOUT tSPOUT tHPOUT tSRSD tHRSD tSLSD tHLSD tPLLD POCLK Low to POUT [15:0] Valid Prop. Delay POUT[15:0] and FP Set-up Time w.r.t. POCLK POUT[15:0] and FP Hold Time w.r.t. POCLK RSDP/N Set-up Time w.r.t. RSCLKP/N RSDP/N Hold Time w.r.t. RSCLKP/N LSDP/N Set-up Time w.r.t. LSCLK LSDP/N Hold Time w.r.t. LSCLK LLCLK Duty Cycle LLCLK Low to LLD Valid Propagation Delay RSCLK/LSCLK Clock Period RSCLK/LSCLK Clock Duty Cycle POUT [15:0] Rise and Fall Time1 Description Min 45 -1 2 2 75 75 75 75 40 -75 400 40 60 1.0 150 60 85 Max 55 +1 Units % ns ns ns ps ps ps ps % ps ps % ns ps
LLD and LLCLK Rise and Fall Time2
1. 20% to 80%; 330 to GND. 2. 20% to 80%; 100 line-to line.
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S3044
Figure 7. Output Timing Diagram
SONET/SDH/ATM OC-48 1:16 RECEIVER
POCLKP tP POUT POUT[15:0], FP tS POUT tH POUT
Figure 8. Receiver Input Timing Diagram
RSCLKP tSRSD RSDP/N tHRSD
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
Figure 9. LLD Output Timing
LLCLKP tPLLD LLD
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SONET/SDH/ATM OC-48 1:16 RECEIVER RECEIVER FRAMING
Figure 10 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF. Both boundaries are recognized upon receipt of the first A2 byte. The third A2 byte is the first data byte to be reported with the correct byte alignment on the outgoing data bus (POUT[15:0]). Concurrently, the frame pulse is set high for one POCLK cycle.
S3044
The frame and byte boundary detection block is activated by the rising edge of OOF, and stays active until the first FP pulse. Figure 11 shows the frame and byte boundary detection activation by a rising edge of OOF, and deactivated by the first FP pulse. Figure 12 shows the frame and byte boundary detection activation by a rising edge of OOF, and deactivated by the FRAMEN input.
Figure 10. Frame and Byte Detection
RECOVERED CLOCK/ REFCLK OOF SERDATI A1 A1 A1 A2 A2 A2 A2 A2 Note 1
POUT[15:0]
A1, A1 Invalid Data
A1, A1
A1, A1
A2, A2
A2, A2
Valid Data POCLK FP
1. Range of input to output delay can be 1.5 to 2.5 POCLK cycles.
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S3044
Figure 11. OOF Timing (FRAMEN = 1)
SONET/SDH/ATM OC-48 1:16 RECEIVER
BOUNDARY DETECTION ENABLED
OOF
FP
SEARCH
Figure 12. FRAMEN Timing
BOUNDARY DETECTION ENABLED
OOF
FRAMEN
FP
SEARCH
Figure 13. Differential Voltage Measurement
Single-ended swing
V SINGLE
V DIFF = 2X Single-ended swing
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Figure 14. +5V Differential PECL Driver to S3044 Input AC Coupled Termination
S3044
+5V .01F 330 Z0=50 Z0=50
Vcc -0.70V (DC AVG)
+3.3V
100
330
.01F
Vcc -0.70V (DC AVG) S3042/44 RSDP/N RSCLKP/N
Figure 15. S3040 to S3042/S3044 Terminations
+5V .01F Z0=50
Vcc -0.70V +3.3V (DC AVG)
100
.01F S3040 SERDATOP/N SERCLKOP/N
Z0=50
Vcc -0.70V (DC AVG) S3042/44 RSDP/N RSCLKP/N
Figure 16. S3044 to S3043 Terminations
+3.3 V 0.01 F Z0=50
3.3 V 1 k 3.3 V 1 k 6.2 k 100
+3.3 V
6.2 k 0.01 F Z0=50 S3044 LLCLKP/N LLDP/N
S3043 LLCLKP/N LLDP/N
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S3044
Figure 17. Single-Ended PECL Output Termination
SONET/SDH/ATM OC-48 1:16 RECEIVER
+3.3 V Z0=50 220
3.3 V 82 130
+3.3 V
S3044 POUTP
LVPECL
Figure 18. Alternative Single-Ended PECL Output Termination
+3.3V Z0=50 220 POUTP 50 0.1F
+3.3V
S3044
LVPECL
Figure 19. Single-Ended PECL Output Termination
Vcc +3.3 V 5600 510 Z0=50
+3.3 V
OVREF S3044 LVPECL
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Figure 20. S3043 to S3044 for Diagnostic Loopback
S3044
+3.3 V
3.3 V 0.01 F Z0=50 1 k 6.2 k 0.01 F Z0=50 3.3 V 1 k 6.2 k 100
+3.3 V
S3043 LSDP/N LSCLKP/N
S3044 LSDP/N LSCLKP/N
Figure 21. Single-Ended LVPECL Driver to S3044 Input AC Coupled Termination
Vcc .01F Z =50 0 300 .01F
Vcc -0.70V (DC AVG)
+3.3V
60 Vcc -0.70V (DC AVG)
Single-Ended Driver
S3044 RSDP/N RSCLKP/N
Figure 22. Differential LVPECL Termination
+3.3V Z0=50 220 220 Z0=50 100
+3.3V
POCLKP/N
LVPECL Differential Input
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S3044
Ordering Information
PREFIX DEVICE
SONET/SDH/ATM OC-48 1:16 RECEIVER
PACKAGE
S - Integrated Circuit
3044
A - 80 PQFP/TEP
X
Prefix
XXXX
Device
X
Package
IS
O 90 0
D
1
IFI
Applied Micro Circuits Corporation 6290 Sequence Drive, San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 2000 Applied Micro Circuits Corporation D205/R334
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December 8, 2000 / Revision H

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